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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com 192 khz stereo dac with 2 vrms line out features ! multi-bit delta-sigma modulator ! 24-bit conversion ! up to 192 khz sample rates ! 112 db dynamic range ! -100 db thd+n ! +3.3 v, +9 to 12 v, and vl power supplies ! 2 vrms output into 5 k ? ac load ! digital volume control with soft ramp ? 119 db attenuation ? 1/2 db step size ? zero crossing click-free transitions ! atapi mixing ! low clock jitter sensitivity ! popguard ? technology for control of clicks and pops description the cs4351 is a complete stereo digital-to-analog sys- tem including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-em- phasis, volume control, chann el mixing, analog filtering, and on-chip 2 vrms line-level driver. the advantages of this architecture include id eal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high toler- ance to clock jitter, and a minimal set of external components. the cs4351 is available in a 20-pin tssop package in both commercial (-10c - +70c) and automotive grades (-40c to +85c). the cdb4351 customer demonstration board is also available for device evalu- ation and implementation suggestions. please see ?ordering information? on page 37 for complete details. these features are ideal fo r cost-sensitive, 2-channel audio systems including dvd players, a/v receivers, set-top boxes, digital tvs and vcrs, mini-component systems, and mixing consoles. pcm ser i al interface interpolation fi l t er wi t h vol ume cont r ol internal voltage ref er ence ex t er n al mute co n t r o l dac e rial audio input left and right mute controls 2 vrms line level right channel output 2 vrms line level left channel outp u reset 8 v to 3.3v dac register/hardware configuration level translator d ware or i 2 c/ spi co n t r o l dat a multibit ? modulator 3.3 v 9 v to 12 v interpolation fi l t er wi t h vol ume cont r ol amp + filter amp + filter aut o speed mode det ect multibit ? modulator december '05 ds566f1 cs4351
2 ds566f1 cs4351 table of contents 1. pin description .......................................................................................................... ..................... 5 2. characteristics and specificat ions ................ ................ ................ ............. ............. ........... 6 specified operating conditions .............................................................................................. 6 absolute maximum ratings ....................................................................................................... .6 dac analog characteristics .................................................................................................... 7 combined interpolation & on-chip analog filter response ......... ................ .............. 8 combined interpolation & on-chip analog filter response ......... ................ .............. 9 switching specifications - serial audio inte rface ............. ................ ................ ......... 10 switching characteristics - control port - i2c ? format ........................................... 11 switching characteristics - control port - spi? format......................................... 12 digital characteristics........................................................................................................ .... 13 power and thermal characteristics ................................................................................. 13 3. typical connection diagram ................................................................................................ .. 14 4. applications .............................................................................................................. .................... 15 4.1 sample rate range/operationa l mode detect ............................................................................ 15 4.1.1 auto-detect enabled ..................................................................................................... ... 15 4.1.2 auto-detect disabled .................................................................................................... ... 15 4.2 system clocking ........................................................................................................... ................ 15 4.3 digital interface format .................................................................................................. .............. 16 4.3.1 stand-alone mode ........................................................................................................ ... 16 4.3.2 control port mode ...................................................................................................... ..... 16 4.4 de-emphasis control ....................................................................................................... ............ 17 4.4.1 stand-alone mode ........................................................................................................ ... 18 4.4.2 control port mode ....................................................................................................... ..... 18 4.5 recommended power-up sequence ........................................................................................... 18 4.5.1 stand-alone mode ........................................................................................................ ... 18 4.5.2 control port mode ....................................................................................................... ..... 18 4.6 popguard ? transient control ....................................................................................................... 18 4.6.1 power-up ................................................................................................................ ......... 18 4.6.2 power-down .............................................................................................................. ...... 19 4.6.3 discharge time .......................................................................................................... ...... 19 4.7 mute control .............................................................................................................. ................... 19 4.8 grounding and power supply ar rangements ............................................................................... 19 4.8.1 capacitor placement ..................................................................................................... ... 19 4.9 control port interface .................................................................................................... ............... 20 4.9.1 map auto increment ...................................................................................................... .. 20 4.9.2 i2c mode ................................................................................................................ .......... 20 4.9.3 spi mode ................................................................................................................ ......... 21 4.10 memory address pointer (map) ............................................................................................. .... 22 4.10.1 incr (auto map increment enable) ........ ...................................................................... 22 4.10.2 map (memory address poin ter) .................................................................................... 22 5. register quick reference .................................................................................................. ..... 23 6. register description ...................................................................................................... ........... 24 6.1 chip id - register 01h .................................................................................................... .............. 24 6.2 mode control 1 - register 02h ............................................................................................. ........ 24 6.2.1 digital interface format (dif2:0) bits 6- 4 ........................................................................ 24 6.2.2 de-emphasis control (dem1:0) bits 3-2. ........................................................................ 24 6.2.3 functional mode (fm) bits 1-0 ......................................................................................... 25 6.3 volume mixing and inversion control - register 03h ................................................................... 25 6.3.1 channel a volume = channel b volume (v olb=a) bit 7 ............................................... 25 6.3.2 invert signal polarity (invert_a) bit 6 .. ............................................................................. 25 6.3.3 invert signal polarity (invert_b) bit 5 .. ............................................................................. 25
ds566f1 3 cs4351 6.3.4 atapi channel mixing and muting (atapi3:0) bits 3-0 .................................................. 26 6.4 mute control - register 04h .............................................................................................. .......... 27 6.4.1 auto-mute (amute) bit 7 ................................................................................................ 2 7 6.4.2 amutec = bmutec (mutec a=b) bit 5 ...................................................................... 27 6.4.3 a channel mute (mute_a) bit 4 b channel mute (mute_b) bit 3 .................................................................................... 27 6.5 channel a volume co ntrol - register 05h channel b volume control - register 06h .......... ...................................................................... 27 6.5.1 digital volume control (vol7:0) bits 7-0 ........................................................................ 28 6.6 ramp and filter control - register 07h ..... ............................................................................... .... 28 6.6.1 soft ramp and zero cross control (szc1:0) bits 7-6 ..................................................... 28 6.6.2 soft volume ramp-up afte r error (rmp_up) bit 5 ......................................................... 29 6.6.3 soft ramp-down before filter mode chang e (rmp_dn) bit 4 ....................................... 29 6.6.4 interpolation filter select (filt_sel) bit 2 ..................................................................... 29 6.7 misc control - register 08h ............................................................................................... ........... 29 6.7.1 power down (pdn) bit 7 ................................................................................................. 3 0 6.7.2 control port enable (cpen) bit 6 .................................................................................... 30 6.7.3 freeze controls (freeze) bit 5 ......................................................................................... 3 0 7. digital filter response plot s ................ ................ ................ ................. ................ .......... .. 31 8. parameter definitions ..................................................................................................... .......... 35 9. package dimensions ....................................................................................................... ........... 36 10. ordering information ..................................................................................................... ........ 37 11. revision history ......................................................................................................... ................ 37 list of figures figure 1. serial input timing ................................................................................................... .................. 10 figure 2. control port timing - i2c format...................................................................................... .......... 11 figure 3. control port timing - spi format (write).............................................................................. ..... 12 figure 4. typical connection diagram............................................................................................ .......... 14 figure 5. left-justified up to 24-bit data...................................................................................... ............. 17 figure 6. i2s, up to 24-bit data ................................................................................................ ................. 17 figure 7. right-justified data.................................................................................................. .................. 17 figure 8. de-emphasis curve................................ ..................................................................... .............. 17 figure 9. control port timing, i2c mode ......................................................................................... .......... 21 figure 10.control port timing, spi mode ........................................................................................ .......... 22 figure 11.de-emphasis curve.................................................................................................... ............... 24 figure 12.atapi block diagram .................................................................................................. .............. 26 figure 13.singl e-speed (fast) stopband rejection............................................................................... ..... 31 figure 14.singl e-speed (fast) transition band .................................................................................. ........ 31 figure 15.single- speed (fast) transition band (detail) ......................................................................... ..... 31 figure 16.single-speed (fast) passband ripple .................................................................................. ...... 31 figure 17.singl e-speed (slow) stopband rejection ............................................................................... ... 31 figure 18.single-speed (slow) transition band.................................................................................. ....... 31 figure 19.single- speed (slow) transition band (detail)....... .................................................................. .... 32 figure 20.singl e-speed (slow) passband ripple.................................................................................. ..... 32 figure 21.double-speed (fas t) stopband rejection ............................................................................... ... 32 figure 22.double-speed (fast) transition band.................................................................................. ....... 32 figure 23.double-speed (fas t) transition band (detail)......................................................................... .... 32 figure 24.double-speed (fast) passband ripple.................................................................................. ..... 32 figure 25.double-spe ed (slow) stopband rejection ............................................................................... .. 33 figure 26.double-spe ed (slow) transition band .................................................................................. ..... 33 figure 27.double-sp eed (slow) transition band (detail) ........ ................................................................. .. 33 figure 28.double-spe ed (slow) passband ripple ..................... ............................................................. ... 33
4 ds566f1 cs4351 figure 29.quad-speed (fast) stopband rejection ................................................................................. .... 33 figure 30.quad-speed (fast) transition band .................................................................................... ....... 33 figure 31.quad-speed (fast) transition band (detail) ........................................................................... .... 34 figure 32.quad-speed (fast) passb and ripple .................................................................................... ..... 34 figure 33.quad-speed (slow) stopband rejection................................................................................. ... 34 figure 34.quad-speed (slow) transition band....... ............................................................................. ...... 34 figure 35.quad-speed (slo w) transition band (det ail)........................................................................... ... 34 figure 36.quad-speed (slow) passband ripple.................................................................................... .... 34 list of tables table 1. cs4351 auto-detect .................................................................................................... ................ 15 table 2. cs4351 mode select .................................................................................................... ............... 15 table 3. single-speed mode standard frequencies ................................................................................ .16 table 4. double-speed mode standard frequencies................................................................................ 16 table 5. quad-speed mode standard frequencies .................................................................................. 16 table 6. digital interface format - stand-alone mode........................................................................... .... 16 table 7. digital interface formats ............................................................................................. ................. 24 table 8. atapi decode .......................................................................................................... ................... 26 table 9. example digital volume settings .......... ............................................................................. .......... 28 table 10. revision history ..................................................................................................... .................... 37
ds566f1 5 cs4351 1. pin description pin name # pin description sdin 1 serial audio data input ( input ) - input for two?s complement serial audio data. sclk 2 serial clock ( input ) - serial clock for the serial audio interface. lrck 3 left / right clock ( input ) - determines which channel, left or right , is currently active on the serial audio data line. mclk 4 master clock ( input ) - clock source for the delta-sigma modulator and digital filters. vd 5 digital power ( input ) - positive power supply for the digital section. gnd 6 16 ground ( input ) - ground reference. rst 10 reset ( input ) - powers down device and resets all internal resisters to their default settings when enabled. va 11 low voltage analog power ( input ) - positive power supply for the analog section. vbias 12 positive voltage reference ( output ) - positive reference voltage for the internal dac. vq 13 quiescent voltage ( output ) - filter connection for internal quiescent voltage. va_h 17 high voltage analog power ( input ) - positive power supply for the analog section. vl 20 serial audio interface power ( input ) - positive power for the serial audio interface bmutec amutec 14 19 mute control ( output ) - control signal for optional mute circuit. aoutb aouta 15 18 analog outputs ( output ) - the full scale analog line output level is specified in the analog character- istics table. control port definitions scl/cclk 7 serial control port clock ( input ) - serial clock for the control port interface. sda/cdin 8 serial control data ( input/output ) - input/output for i2c data. input for spi data. ad0/cs 9 address bit 0 / chip select ( input ) - chip address bit in i2c mode. control port enable in spi mode. stand-alone definitions dif0 dif1 8 7 digital interface format ( input ) - defines the required relationship between the left right clock, serial clock, and serial audio data. dem 9 de-emphasis ( input ) - selects the standard 15 s/50 s digital de-emphasis filter response for 44.1 khz sample rates sdin vl sclk amutec lrck aouta mclk va_h vd gnd gnd aoutb dif1(scl/cclk) bmutec dif0(sda/cdin) vq dem(ad0/cs ) vbias rst va 1 2 3 4 5 6 7 8 9 10 11 12 17 18 19 20 13 14 15 16
6 ds566f1 cs4351 2. characteristics a nd specifications (min/max performance characteristics and specifications are guaranteed over the spec ified operating conditions. typical specifications are derived from performance measurements at t a = 25 c, va_h = 12 v, va = 3.3 v, vd = 3.3 v.) specified operating conditions (gnd = 0 v; all voltages with respect to ground.) absolute maximum ratings (gnd = 0 v; all voltages with respect to ground.) operation at or beyond these limits may result in permane nt damage to the device. normal operation is not guar- anteed at these extremes. parameters symbol min typ max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l 8.55 3.13 3.13 1.7 12 3.3 3.3 3.3 12.6 3.47 3.47 3.47 v v v v specified temperature range -czz -dzz t a t a -10 -40 - - 70 85 c c parameters symbol min max units dc power supply high voltage analog power low voltage analog power digital power interface power v a_h v a v d v l -0.3 -0.3 -0.3 -0.3 14 3.63 3.63 3.63 v v v v input current, any pin except supplies i in -10ma digital input voltage digital interface v in-l -0.3 v l + 0.4 v ambient operating temperature (power applied) t a -55 125 c storage temperature t stg -65 150 c
ds566f1 7 cs4351 dac analog characteristics (test conditions (unless otherwise spec ified): input test signal is a 997 hz sine wave at 0 dbfs; measurement bandwidth 10 hz to 20 khz) notes: 1. one-half lsb of triangular pdf dither is added to data. parameter symbol min typ max unit all speed modes fs = 48, 96, and 192 khz dynamic range (note 1) 24-bit unweighted a-weighted 16-bit unweighted a-weighted 99 102 - - 109 112 95 98 - - - - db db db db total harmonic distortion + noise (note 1) 24-bit 0 db -20 db -60 db 16-bit 0 db -20 db -60 db thd+n - - - - - - - -100 -89 -49 -92 -75 -35 -90 -79 -39 - - - db db db db db db all speed modes idle channel noise / signal-to-noise ratio - 109 - db interchannel isolation (1 khz) - 100 - db analog output - all modes full scale output voltage 1.85 2.00 2.15 vrms common mode voltage v q -4-vdc max dc current draw from an aout pin i outmax -10- a max current draw from vq i qmax -1- a interchannel gain mismatch - 0.1 - db gain drift - -100 - ppm/c output impedance z out -50- ? ac-load resistance r l 5--k ? load capacitance c l --100pf
8 ds566f1 cs4351 combined interpolat ion & on-chip analog filter response (the filter characteristics have been normalized to the sa mple rate (fs) and can be re ferenced to th e desired sam- ple rate by multiplying the given characteristic by fs. see (note 6) parameter fast roll-off unit min typ max combined digital and on-chip analog filter response - single-speed mode - 48 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .454 .499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband 0.547 - - fs stopband attenuation (note 4) 102 - - db total group delay (fs = output sample rate) - 9.4/fs - s intra-channel phase deviation - - 0.56/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 5) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db combined digital and on-chip analog filt er response - double-speed mode - 96 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .430 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .583 - - fs stopband attenuation (note 4) 80 - - db total group delay (fs = output sample rate) - 4.6/fs - s intra-channel phase deviation - - 0.03/fs s inter-channel phase deviation - - 0 s combined digital and on-chip analog filter response - quad-speed mode - 192 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - .105 .490 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .635 - - fs stopband attenuation (note 4) 90 - - db total group delay (fs = output sample rate) - 4.7/fs - s intra-channel phase deviation - - 0.01/fs s inter-channel phase deviation - - 0 s
ds566f1 9 cs4351 combined interpolation & on-c hip analog filter response (continued) notes: 2. slow roll-off interpolation filter is only available in control port mode. 3. response is clock dependent and will scale with fs. 4. for single-speed mode, the measurement bandwidth is from stopband to 3 fs. for double-speed mode, the measurement bandwidth is from stopband to 3 fs. for quad-speed mode, the measurement bandwidth is from stopband to 1.34 fs. 5. de-emphasis is available only in single-speed mode; only 44.1 khz de-emphasis is available in stand- alone mode. 6. amplitude vs. frequency plots of this data are available in the ?digital filter response plots? on page 31 . parameter slow roll-off (note 2 ) unit min typ max single-speed mode - 48 khz passband (note 3) to -0.01 db corner to -3 db corner 0 0 - - 0.417 0.499 fs fs frequency response 10 hz to 20 khz -0.01 - +0.01 db stopband .583 - - fs stopband attenuation (note 4) 64 - - db total group delay (fs = output sample rate) - 6.5/fs - s intra-channel phase deviation - - 0.14/fs s inter-channel phase deviation - - 0 s de-emphasis error (note 5) fs = 32 khz (relative to 1 khz) fs = 44.1 khz fs = 48 khz - - - - - - 0.23 0.14 0.09 db db db double-speed mode - 96 khz passband (note 3) ) to -0.01 db corner to -3 db corner 0 0 - - .296 .499 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .792 - - fs stopband attenuation (note 4) 70 - - db total group delay (fs = output sample rate) - 3.9/fs - s intra-channel phase deviation - - 0.01/fs s inter-channel phase deviation - - 0 s quad-speed mode - 192 khz passband (note 3) ) to -0.01 db corner to -3 db corner 0 0 - - .104 .481 fs fs frequency response 10 hz to 20 khz -0.01 - 0.01 db stopband .868 - - fs stopband attenuation (note 4) 75 - - db group delay - 4.2/fs - s intra-channel phase deviation - 0.01/fs s inter-channel phase deviation - - 0 s
10 ds566f1 cs4351 switching specificatio ns - serial audio interface parameters symbol min max units mclk frequency 1.024 51.2 mhz mclk duty cycle 45 55 % input sample rate (manual selection) single-speed mode double-speed mode quad-speed mode fs fs fs 4 50 100 50 100 200 khz khz khz input sample rate (auto selection) single-speed mode double-speed mode quad-speed mode fs fs fs 4 84 170 50 100 200 khz khz khz lrck duty cycle 40 60 % sclk pulse width low t sclkl 20 - ns sclk pulse width high t sclkh 20 - ns sclk period single-speed mode t sclkw -- double-speed mode t sclkw -- quad-speed mode t sclkw -- sclk rising to lrck edge delay t slrd 23 - ns sclk rising to lrck edge setup time t slrs 20 - ns sdin valid to sclk rising setup time t sdlrs 20 - ns sclk rising to sdin hold time t sdh 20 - ns 1 128 () fs --------------------- - 1 64 () fs ------------------ 2 mclk ----------------- sclkh t slrs t slrd t sdlrs t sdh t sclkl t sdata sclk lrck figure 1. serial input timing
ds566f1 11 cs4351 switching characteristics - control port - i2c ? format (inputs: logic 0 = gnd, logic 1 = vl, c l =20pf) notes: 7. data must be held for sufficient ti me to bridge the transition time, t fc , of scl. parameter symbol min max unit scl clock frequency f scl - 100 khz rst rising edge to start t irs 500 - ns bus free time between transmissions t buf 4.7 - s start condition hold time (prior to first clock pulse) t hdst 4.0 - s clock low time t low 4.7 - s clock high time t high 4.0 - s setup time for repeated start condition t sust 4.7 - s sda hold time from scl falling (note 7) t hdd 0-s sda setup time to scl rising t sud 250 - ns rise time of scl and sda t rc , t rc -1s fall time scl and sda t fc , t fc -300ns setup time for stop condition t susp 4.7 - s acknowledge delay from scl falling t ack 300 1000 ns t buf t hdst t low t hdd t high t sud stop start sda scl t irs rst t hdst t rc t fc t sust t sus p start stop repeated t rd t fd t ack figure 2. control port timing - i2c format
12 ds566f1 cs4351 switching characteristics - control port - spi ? format (inputs: logic 0 = gnd, logic 1 = vl, c l =20pf) notes: 8. t spi only needed before first falling edge of cs after rst rising edge. t spi = 0 at all other times. 9. data must be held for sufficient time to bridge the transition time of cclk. 10. for f sck < 1 mhz. parameter symbol min max unit cclk clock frequency f sclk -6mhz rst rising edge to cs falling t srs 500 - ns cclk edge to cs falling (note 8) t spi 500 - ns cs high time between transmissions t csh 1.0 - s cs falling to cclk edge t css 20 - ns cclk low time t scl 66 - ns cclk high time t sch 66 - ns cdin to cclk rising setup time t dsu 40 - ns cclk rising to data hold time (note 9) t dh 17 - ns rise time of cclk and cdin (note 10) t r2 - 100 ns fall time of cclk and cdin (note 10) t f2 - 100 ns t r2 t f2 t dsu t dh t sch t scl cs cclk cdin t css t csh t spi t srs rst figure 3. control port timing - spi format (write)
ds566f1 13 cs4351 digital characteristics power and thermal characteristics notes: 11. current consumption increases with increasing fs and increasing mclk. typ and max values are based on highest fs and highest mclk. variance between speed modes is small. 12. i l measured with no external loading on pin 8 (sda). 13. power-down mode is defined as res pin = low with all clock an d data lines held static. 14. valid with the recommended capacitor values on vq and v bias as shown in the typical connection dia- gram in section 3 . parameters symbol min typ max units high-level input voltage vl = 3.3 v vl = 2.5 v vl = 1.8 v v ih v ih v ih 2.0 1.7 0.65?v l - - - - - - v v v low-level input voltage vl = 3.3 v vl = 2.5 v vl = 1.8 v v il v il v il - - - - - - 0.8 0.7 0.33?v l v v v input leakage current i in --10 a input capacitance - 8 - pf maximum mutec drive current - 2 - ma mutec high-level output voltage v oh -va_h- v mutec low-level output voltage v ol -0- v parameters symbol min typ max units power supplies power supply current normal operation, v a_h = 12 v (note 11) v a_h = 9 v v a = 3.3 v v d = 3.3 v interface current (note 12) v l = 3.3 v power-down state, all supplies (note 13) i a_h i a_h i a i d i l i pd - - - - - - 15 14 6 21 100 200 20 19 8 26 400 - ma ma ma ma a a power dissipation (all supplies) (note 11) va_h = 12 v normal operation power-down (note 13) va_h = 9 v normal operation power-down (note 13) - - - - 270 1 216 1 354 - 285 - mw mw mw mw power supply rejection ratio (note 14) (1 khz) (60 hz) psrr - - 60 60 - - db db
14 ds566f1 cs4351 3. typical connection diagram 16 digital audio source vl gnd cs4351 mclk vd aouta 1 17 0.1 f + 10 f +3.3 v * c/ mode configuration 9 10 8 sdin 2 dif1(scl/cclk) dif0(sda/cdin) dem(ad0/cs) optional mute circuit rst bmutec 3.3 f aouta + + 12 13 vbias+ vq 7 4 3 lrck sclk 3.3 f 10 k ? 560 ? + 14 18 3.3 f 10k ? 560 ? + 15 aoutb 3.3 f va_h 0.1 f + 10 f gnd 6 0.1 f +1.8 v to vd +9 v to +12 v 5 20 amutec 19 va 11 0.1 f + 10 f +3.3 v 5.1 ?? 2.2 nf* 2.2 nf* *optional *shown value is for fc=130khz *remove this supply if optional resistor is present. the decoupling caps should remain. 576 k ? 412 k ? optional mute circuit aouta 576 k ? 412 k ? figure 4. typical connection diagram
ds566f1 15 cs4351 4. applications 4.1 sample rate range/ope rational mode detect the device operates in one of three operat ional modes. the allowed sample rate range in each mode will depend on whether the auto-detect de feat bit is enabled/disabled. 4.1.1 auto-detect enabled the auto-detect feature is enabled by default. in this state, the cs4351 will auto-detect the correct mode when the input sample rate (f s ), defined by the lrck frequency, fa lls within one of the ranges illustrated in table 1 . sample rates outside the specified r ange for each mode are not supported. 4.1.2 auto-detect disabled the auto-detect feature can be defeat ed only by the format bits in the control port register 02h. in this state, the cs4351 will not auto- detect the corr ect mode based on the in put sample rate (f s ). the opera- tional mode must then be set manually accordi ng to one of the ranges illustrated in table 2 . please refer to section 6.2.3 for implementation details. sample rates outside the specified range for each mode are not supported. in stand-alone mode it is not possible to disable auto-detect of sample rates. 4.2 system clocking the device requires external generati on of the master (mclk), left/right (lrck) and serial (sclk) clocks. the left/right clock, defined also as the input sample rate (f s ), must be synchronously derived from the mclk according to specified ratios. the specified rati os of mclk to lrck, along with several standard au- dio sample rates and the required mc lk frequency, ar e illustrated in tables 3 through 5 . refer to section 4.3 for the required sclk timing associated with the selected digital interface format and to the ?switching specifications - serial audio interface? section on page 10 for the maximum allowed clock frequencies. input sample rate (f s )mode 4 khz - 50 khz single-speed mode 84 khz - 100 khz double-speed mode 170 khz - 200 khz quad-speed mode table 1. cs4351 auto-detect fm1 fm0 input sample rate (f s )mode 0 0 auto speed mode detect auto 0 1 4 khz - 50 khz single-speed mode 1 0 50 khz - 100 khz double-speed mode 1 1 100 khz - 200 khz quad-speed mode table 2. cs4351 mode select
16 ds566f1 cs4351 4.3 digital interface format the device will accept audio samples in 1 of 4 digital interface formats in stand- alone mode, as illustrated in table 6 , and 1 of 6 formats in contro l port mode, as illustrated in table 7 . 4.3.1 stand-alone mode the desired format is selected via th e dif1 and dif0 pins. for an illustration of th e required relationship between the lrck, sclk and sdin, see figures 5 through 7 . for all formats, sdin is valid on the rising edge of sclk. also, sclk must have at least 32 c ycles per lrck period in format 2, and 48 cycles per lrck period in format 3. 4.3.2 control port mode the desired format is selected via the dif2, dif1 and di f0 bits in the mode control 2 register (see section section 6.2.1 ). for an illustration of the required relationship betwee n lrck, sclk and sdin, see figures 5 through 7 . for all formats, sdin is valid on the risi ng edge of sclk. also, sclk must have at sample rate (khz) mclk (mhz) 256x 384x 512x 768x 1024x 1152x 32 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 44.1 11.2896 16.9344 22.5792 33.8688 45.1584 48 12.2880 18.4320 24.5760 36.8640 49.1520 table 3. single-speed mode standard frequencies sample rate (khz) mclk (mhz) 128x 192x 256x 384x 512x 64 8.1920 12.2880 16.3840 24.5760 32.7680 88.2 11.2896 16.9344 22.5792 33.8688 45.1584 96 12.2880 18.4320 24.5760 36.8640 49.1520 table 4. double-speed mode standard frequencies sample rate (khz) mclk (mhz) 64x 96x 128x 192x 256x 176.4 11.2896 16.9344 22.5792 33.8688 45.1584 192 12.2880 18.4320 24.5760 36.8640 49.1520 table 5. quad-speed mode standard frequencies = denotes clock modes which are not auto detected dif0 dif1 description format figure 00 i 2 s, up to 24-bit data 0 6 01 left justified, up to 24-bit data 1 5 10 right justified, 24-bit data 2 7 11 right justified, 16-bit data 3 7 table 6. digital interface format - stand-alone mode
ds566f1 17 cs4351 least 32 cycles per lrck period in format 2, 48 cycle s in format 3, 40 cycles in format 4, and 36 cycles in format 5. 4.4 de-emphasis control the device includes on-chip digital de-emphasis. figure 8 shows the de-emphasis curve for f s equal to 44.1 khz. the frequency response of th e de-emphasis curve will scale propor tionally with changes in sample rate, fs. note: de-emphasis is only availa ble in single-speed mode. lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 lsb msb lsb figure 5. left-justifi ed up to 24-bit data lrck sclk left channel right channel sdin +3 +2 +1 +5 +4 msb -1 -2 -3 -4 -5 +3 +2 +1 +5 +4 -1 -2 -3 -4 msb lsb lsb figure 6. i2s, up to 24-bit data lrck sclk left channel sdin -6 -5 -4 -3 -2 -1 -7 +1 +2 +3 +4 +5 msb right channel lsb msb +1 +2 +3 +4 +5 lsb -6 -5 -4 -3 -2 -1 -7 msb figure 7. right-justified data gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz figure 8. de-emphasis curve
18 ds566f1 cs4351 4.4.1 stand-alone mode when pulled to vl the dem pin activates the 44.1 khz de-emphasis filter. when pulled to gnd the dem pin turns off the de-emphasis filter. 4.4.2 control port mode the mode control bits selects either the 32, 44.1, or 48 khz de-emphasis filter. please see section 6.2.2 for the desired de-emphasis control. 4.5 recommended power-up sequence 4.5.1 stand-alone mode 1. hold rst low until the power supp lies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2 . in this state, the control port is reset to its default settings, vq will remain low, and vbias will be connected to va. 2. bring rst high. the device will remain in a low power state with vq low and will initiate the stand- alone power-up sequence after approximately 51 2 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). 4.5.2 control port mode 1. hold rst low until the power supply is stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in section 4.2 . in this state, the control port is reset to its default settings, vq will remain lo w, and vbias will be connected to va. 2. bring rst high. the device will remain in a low power state with vq low. 3. perform a control port write to the cp_en bit pr ior to the completion of approximately 512 lrck cycles in single-speed mode (1024 lrck cycles in double-speed mode, and 2048 lrck cycles in quad-speed mode). the desired register settings can be loaded while keeping the pdn bit set to 1. 4. set the pdn bit to 0. this will initiate the powe r-up sequence, which lasts approximately 50 s when the popg bit is set to 0. if the popg bit is set to 1, see section 4.6 for a complete description of power-up timing. 4.6 popguard ? transient control the cs4351 uses a novel technique to minimize the ef fects of output transients during power-up and power- down. this technology, when used with external dc-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by si ngle-ended single-supply conv erters. it is activated inside the dac when the rst pin is toggled and requires no other exte rnal control, aside from choosing the appropriate dc-blocking capacitors. 4.6.1 power-up when the device is initially po wered-up, the audio outputs, aout a and aoutb, are clamped to gnd. following a delay of approximately 1000 sample periods, each output begins to ramp toward the quies- cent voltage. approximat ely 10,000 lrck cycles late r, the outputs reach v q and audio output begins. this gradual voltage rampin g allows time for the external dc-blocki ng capacitors to charge to the quies- cent voltage, minimizing audible power-up transients.
ds566f1 19 cs4351 4.6.2 power-down to prevent audible transients at power-down, the devi ce must first enter its power-down state. when this occurs, audio output ceases and the internal out put buffers are disconnected from aouta and aoutb. in their place, a soft-start current sink is substitute d which allows the dc-blocking capacitors to slowly dis- charge. once this charge is dissipated, the power to the device may be turned off and the system is ready for the next power-on. 4.6.3 discharge time to prevent an audio transient at the next power-on , the dc-blocking capacitors must fully discharge be- fore turning on the power or exitin g the power-down state. if full disc harge does not occur, a transient will occur when the audio outputs are initially clamped to gnd. the time that the device must remain in the power-down state is related to the value of the dc-bl ocking capacitance and the output load. for example, with a 3.3 f capacitor, the minimum power-do wn time will be approximately 0.4 seconds. 4.7 mute control the mute control pins go active during power-up initialization, reset, muting (see section 6.4.3 ), or if the mclk to lrck ratio is incorrect. these pins are intend ed to be used as control for external mute circuits to prevent the clicks and pops t hat can occur in any single-e nded single supply system. use of the mute control function is not mandatory but recommended for designs requiring the absolute min- imum in extraneous clicks and pops. also, use of th e mute control function can enable the system designer to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit. please see the ?typical connection diagram? on page 14 for a suggested mute circ uit for single supply sys- tems. this fet circuit must be placed in series after the rc filter, otherwise noise may occur during muting conditions. further esd protection will need to be ta ken into consideration for th e fet used. if dual supplies are available, the bjt mute circuit from figure 12 in the cs4398 datasheet (active low) may be used. 4.8 grounding and power supply arrangements as with any high resolution converter, the cs4351 re quires careful attention to power supply and grounding arrangements if its potential performance is to be realized. figure 4 shows the recommended power ar- rangements, with va_h, va, vd, and vl connected to cl ean supplies. if the ground planes are split between digital ground and analog ground, the gnd pins of the cs4351 should be connected to the analog ground plane. all signals, especially clocks, should be kept away from the vbias and vq pins in order to avoid unwanted coupling into the dac. 4.8.1 capacitor placement decoupling capacitors should be placed as close to the dac as possible, with the low value ceramic ca- pacitor being the closest. to further minimize imped ance, these capacitors should be located on the same layer as the dac. if desired, all supply pins may be connected to the same supply, but a decoupling ca- pacitor should still be placed on each supply pin. note: all decoupling capacitors should be referenced to analog ground. the cdb4351 evaluation board demonstrates the op timum layout and power supply arrangements.
20 ds566f1 cs4351 4.9 control port interface the control port is used to load all the internal register settings (see section 6 ). the operation of the control port may be completely asynchronous with the audio sa mple rate. however, to avoid potential interference problems, the control port pins should remain static if no operation is required. the control port operates in one of two modes: i2c or spi. 4.9.1 map auto increment the device has map (memory address pointer) auto increment capability enabled by the incr bit (also the msb) of the map. if incr is set to 0, map will stay constant for successive i2c writes or reads and spi writes. if incr is set to 1, map will auto incremen t after each byte is wri tten, allowing block reads or writes of successive registers. 4.9.2 i2c mode in the i2c mode, data is clocked into and out of the bi -directional serial control data line, sda, by the serial control port clock, scl (see figure 9 for the clock to data relationship). there is no cs pin. pin ad0 en- ables the user to alter the chip address (100110[ad0][r/w ]) and should be tied to vl or gnd as required, before powering up the device. if the device ever detects a high to low transition on the ad0/cs pin after power-up, spi mode will be selected. 4.9.2.1 i2c write to write to the device, follow the procedure below wh ile adhering to the control port switching specifica- tions in section 8 . 1. initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 100110. the seventh bit must match the setting of the ad0 pin, and the eigh th must be 0. the eighth bit of the address byte is the r/w bit. 2. wait for an acknowledge (ack) from the part, then write to the memory address pointer, map. this byte points to the regi ster to be written. 3. wait for an acknowledge (ack) from the part, then write the desired data to the register pointed to by the map. 4. if the incr bit (see section 4.9.1 ) is set to 1, repeat the previous step until all the desired registers are written, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i2c writes to other registers are desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from step 1. if no further writes to oth- er registers are desired, initiate a stop condition to the bus.
ds566f1 21 cs4351 4.9.2.2 i2c read to read from the device, follow the procedure below while adhering to the control port switching specifica- tions. 1. initiate a start condition to the i2c bus followed by the address byte. the upper 6 bits must be 100110. the seventh bit must match the setting of t he ad0 pin, and the eighth must be 1. the eighth bit of the address byte is the r/w bit. 2. after transmitting an acknowledg e (ack), the device will then transm it the contents of the register pointed to by the map. the map re gister will contain the address of the last register written to the map, or the default address (see section 4.10.2 ) if an i2c read is the first operation performed on the device. 3. once the device has transmitted the contents of the register pointed to by the map, issue an ack. 4. if the incr bit is set to 1, the device will continue to transmit the contents of successive registers. continue providing a clock and issue an ack after each byte until all the desired registers are read, then initiate a stop condition to the bus. 5. if the incr bit is set to 0 and further i2c reads from other registers are desired, it is necessary to initiate a repeated start condition and follow the procedure detailed from steps 1 and 2 from the i2c write instructions followed by step 1 of the i2c read section. if no further reads from other reg- isters are desired, initiate a stop condition to the bus. 4.9.3 spi mode in spi mode, data is clocked into the serial control data line, cdin, by the serial control port clock, cclk (see figure 10 for the clock to data relationshi p). there is no ad0 pin. pin cs is the chip select signal and is used to control spi writes to the control port. when the device detects a high to low transition on the ad0/cs pin after power-up, spi m ode will be selected. all signals are in puts and data is clocked in on the rising edge of cclk. 4.9.3.1 spi write to write to the device, follow the pr ocedure below while adhering to th e control port switching specifica- tions in section 8 . 1. bring cs low. 2. the address byte on the cdin pin must then be 10011000. 3. write to the memory address pointer, map. th is byte points to the register to be written. sda scl 100110 ad0 r/w start ack data 1-8 ack data 1-8 ack stop note note: if operation is a write, this byte contains the memory address pointer, map. if operation is a read, this byte contains the data of the register pointed to by the map. figure 9. control port timing, i2c mode
22 ds566f1 cs4351 4. write the desired data to the register pointed to by the map. 5. if the incr bit (see section 4.9.1 ) is set to 1, repeat the previous step until all the desired registers are written, then bring cs high. 6. if the incr bit is set to 0 and further spi writes to other registers are desired, it is necessary to bring cs high, and follow the procedure detailed from step 1. if no further writes to other registers are de- sired, bring cs high. ) 4.10 memory addr ess pointer (map) 4.10.1 incr (auto map increment enable) default = ?0? 0 - disabled 1 - enabled 4.10.2 map (memory address pointer) default = ?0000? 76543210 incr reserved reserved reserved map3 map2 map1 map0 00000000 map msb lsb data byte 1 byte n r/w map = memory address pointer address chip cdin cclk cs 1001100 figure 10. control port timing, spi mode
ds566f1 23 cs4351 5. register qu ick reference addr function 7 6 5 4 3 2 1 0 1h chip id part4 part3 part2 part1 part0 rev2 rev1 rev0 default 1 1 1 1 1 - - - 2h mode control reserved dif2 dif1 dif0 dem1 dem0 fm1 fm0 default000 0 0 000 3h volume, mixing, and inversion control volb=a inverta invertb reserved atapi3 atapi2 atapi1 atapi0 default000 0 1 001 4h mute control amute reserved mutec a=b mute_a mute_b reserved reserved reserved default100 0 0 000 5h channel a volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default000 0 0 000 6h channel b volume control vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 default000 0 0 000 7h ramp and filter control szc1 szc0 rmp_up rmp_dn reserved filt_sel reserved reserved default101 1 0 001 8h misc. control pdn cpen freeze reserved reserved reserved reserved reserved default100 0 0 000
24 ds566f1 cs4351 6. register description ** all register access is r/w unless specified otherwise** 6.1 chip id - register 01h function: this register is read-only. bits 7 through 3 are the part number id which is 11111b and the remaining bits (2 through 0) are for the chip revision (rev. a = 000, rev. b = 001, ...) 6.2 mode control 1 - register 02h 6.2.1 digital interface fo rmat (dif2:0) bits 6-4 function: these bits select the interface fo rmat for the serial audio input. the required relationship between the left/right clock, se rial clock and serial data is defined by the digital interface format and the options are detailed in figures 5 through 7 . 6.2.2 de-emphasis control (dem1:0) bits 3-2 . default = 0 00 - no de-emphasis 01 - 44.1 khz de-emphasis 10 - 48 khz de-emphasis 11 - 32 khz de-emphasis function: selects the appropriate digital filter to maintain the stan- dard 15 s/50 s digital de-emphasis filter response at 32, 44.1 or 48 khz sample rates. (see figure 11 .) note: de-emphasis is only available in single-speed mode 76543210 part4 part3 part2 part1 part0 rev2 rev1 rev0 11111 - - - 76543210 reserved dif2 dif1 dif0 dem1 dem0 fm1 fm0 00000000 dif2 dif1 dif0 description format figure 000 left justified, up to 24-bit data 0 (default) 5 001 i 2 s, up to 24-bit data 1 6 010 right justified, 16-bit data 2 7 011 right justified, 24-bit data 3 7 100 right justified, 20-bit data 4 7 101 right justified, 18-bit data 5 7 110 reserved 111 reserved table 7. digital interface formats figure 11. de-emphasis curve gain db -10db 0db frequency t2 = 15 s t1=50 s f1 f2 3.183 khz 10.61 khz
ds566f1 25 cs4351 6.2.3 functional mode (fm) bits 1-0 default = 00 00 - auto speed mode detect 01 - single-speed mode (4 to 50 khz sample rates) 10 - double-speed mode (50 to 100 khz sample rates) 11 - quad-speed mode (100 to 200 khz sample rates) function: selects the required range of input sample rates or dsd mode. 6.3 volume mixing and inversion control - register 03h 6.3.1 channel a volume = cha nnel b volume (volb=a) bit 7 function: when set to 0 (default) the aouta and aoutb volume levels are independently controlled by the a and the b channel volume control bytes. when set to 1 the volume on both aouta and aout b are determined by the a channel attenuation and volume control bytes, and the b channel bytes are ignored. 6.3.2 invert signal polari ty (invert_a) bit 6 function: when set to 1, this bit inverts the signal polarity of channel a. when set to 0 (default), this function is disabled. 6.3.3 invert signal polari ty (invert_b) bit 5 function: when set to 1, this bit inverts the signal polarity of channel b. when set to 0 (default), this function is disabled. b7 b6 b5 b4 b3 b2 b1 b0 volb=a invert a invert b reserved atapi3 atapi2 atapi1 atapi0 00001001
26 ds566f1 cs4351 6.3.4 atapi channel mixing and muting (atapi3:0) bits 3-0 default = 1001 - aouta=al, aoutb=br (stereo) function: the cs4351 implements the channel mixing function s of the atapi cd-rom specification. refer to table 8 and figure 12 for additional information. atapi3 atapi2 atapi1 atapi0 aouta aoutb 0 0 0 0 mute mute 0001 mute br 0010 mute bl 0 0 1 1 mute b[(l+r)/2] 0100 ar mute 0101 ar br 0110 ar bl 0 1 1 1 ar b[(l+r)/2] 1000 al mute 1001 al br 1010 al bl 1 0 1 1 al b[(l+r)/2] 1 1 0 0 a[(l+r)/2] mute 1 1 0 1 a[(l+r)/2] br 1 1 1 0 a[(l+r)/2] bl 1 1 1 1 a[(l+r)/2] b[(l+r)/2] table 8. atapi decode ? a channel volume control aouta aoutb left channel audio data right channel audio data b channel volume control mute mute figure 12. atapi block diagram
ds566f1 27 cs4351 6.4 mute control - register 04h 6.4.1 auto-mute (amute) bit 7 function: when set to 1 (default), the digital-to-analog conver ter output will mute followi ng the reception of 8192 consecutive audio samples of static 0 or -1. a single sample of non- static data will release the mute. de- tection and muting is done independently for each ch annel. the quiescent voltage on the output will be retained and the mute control pin will go active du ring the mute period. when set to 0, this function is disabled 6.4.2 amutec = bmutec (mutec a=b) bit 5 function: when set to 0 (default), the amutec and bmutec pins operate independently. when set to 1, the individual controls for amutec and bmutec are internally connected through an and gate prior to the output pins. therefore, the extern al amutec and bmutec pins will go active only when the requirements for both amutec a nd bmutec are valid. 6.4.3 a channel mute (mute_a) bit 4 b channel mute (mute_b) bit 3 function: when set to 1, the digital-to-anal og converter output will mute. the quiescent volt age on the output will be retained. the muting function is effected, similar to attenuation changes, by the soft and zero cross bits in the volume and mixing co ntrol register. the co rresponding mutec pin w ill go active following any ramping due to the soft and zero cross function. when set to 0 (default), this function is disabled. 6.5 channel a volume control - register 05h channel b volume cont rol - register 06h 76543210 amute reserved mutec a=b mute_a mute_b reserved reserved reserved 10000000 76543210 vol7 vol6 vol5 vol4 vol3 vol2 vol1 vol0 00000000
28 ds566f1 cs4351 6.5.1 digital volume control (vol7:0) bits 7-0 default = 00h (0 db) function: the digital volume control register s allow independent control of the si gnal levels in 1/2 db increments from 0 to -127.5 db. volume settings are decoded as shown in table 9 . the volume changes are imple- mented as dictated by the soft and zero cross bits in the power and muting control register. the actual attenuation is determined by taking the decimal value of the volume register and multiplying by 6.02/12. 6.6 ramp and filter c ontrol - register 07h 6.6.1 soft ramp and zero cros s control (szc1: 0) bits 7-6 default = 10 function: immediate change when immediate change is sele cted all level changes will take ef fect immediately in one step. zero cross zero cross enable dictates that signal level changes, either by attenuation chan ges or muting, will occur on a signal zero crossing to minimize audible arti facts. the requested level change will occur after a time- out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossing. the zero cross function is independently monitored and implemented for each channel. soft ramp pcm soft ramp allows level changes, bo th muting and attenuation, to be implemented by incrementally ramp- ing, in 1/8 db steps, from the current level to the new level at a rate of 1 db per 8 left/right clock periods. binary code decimal value volume setting 00000000 0 0 db 00000001 1 -0.5 db 00000110 6 -3.0 db 11111111 255 - 127.5 db table 9. example digital volume settings 76543210 szc1 szc0 rmp_up rmp_dn reserved filt_sel reserved reserved 10110001 szc1 szc0 description 0 0 immediate change 01 zero cross 10 soft ramp 1 1 soft ramp on zero crossings
ds566f1 29 cs4351 soft ramp and zero cross soft ramp and zero cross enable dictate that signal le vel changes, either by attenuation changes or mut- ing, will occur in 1/8 db steps and be implemen ted on a signal zero crossing. the 1/8 db level change will occur after a time-out period between 512 and 1024 sa mple periods (10.7 ms to 21.3 ms at 48 khz sample rate) if the signal does not encounter a zero crossi ng. the zero cross function is independently monitored and implemented for each channel. 6.6.2 soft volume ramp-up after error (rmp_up) bit 5 function: when set to 1 (default), an un-mute will be perf ormed after executing a f ilter mode change, after a lrck/mclk ratio change or error, and after changing t he functional mode. this un-mute is affected, sim- ilar to attenuation changes, by the soft and zero cro ss bits in the volume and mixing control register. when set to 0, an immediate un-mut e is performed in these instances. note: for best results, it is recommended this featur e be used in conjunction with the rmp_dn bit. 6.6.3 soft ramp-down before filter mode change (rmp_dn) bit 4 function: when set to 1 (default), a mute will be performed prior to executi ng a filter mode change. this mute is affected, similar to attenuation change s, by the soft and zero cross bits in the volume and mixing control register. when set to 0, an immediate mute is perfor med prior to executing a filter mode change. note: for best results, it is recommen ded that this feature be used in conjunction with the rmp_up bit. 6.6.4 interpolation filter select (filt_sel) bit 2 function: when set to 0 (default), the interpol ation filter has a fast roll off. when set to 1, the interpolation filter has a slow roll off. the specifications for each filter can be found in the ?combined interpolation & on-chip analog filter re- sponse? section on page 8 , and response plots can be found in figures 15 to 36 . 6.7 misc control - register 08h 76543210 pdn cpen freeze reserved reserved reserved reserved reserved 10000000
30 ds566f1 cs4351 6.7.1 power down (pdn) bit 7 function: when set to 1 (default), the entire device will enter a low-power state and the contents of the control reg- isters will be retained. the power-do wn bit defaults to ?1? on power- up and must be di sabled before normal operation in control port mode can occur. this bit is ignored if cpen is not set. 6.7.2 control port enable (cpen) bit 6 function: this bit is set to 0 by default, allowing the device to power-up in stand-alo ne mode. control port mode can be accessed by setting this bit to 1. this will allow operation of th e device to be controlled by the reg- isters and the pin definitions will conform to cont rol port mode. 6.7.3 freeze controls (freeze) bit 5 function: when set to 1, this function allo ws modifications to be made to the registers without the changes taking effect until freeze is set back to 0. to make multiple changes in the control port registers take effect simultaneously, enable the freeze bit, make a ll register changes, then disable the freeze bit. when set to 0 (default), register changes take effect immediately.
ds566f1 31 cs4351 7. digital filter response plots 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 13. single-speed (fast) stopband rejectio n figure 14. single-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 15. single-speed (fast) transition band (detail) figure 16. single-speed (fast) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 ?120 ?100 ?80 ?60 ?40 ?20 0 frequency(normalized to fs) amplitude (db) figure 17. single-speed (slow) stopband rejection figure 18. sing le-speed (slow) transition band
32 ds566f1 cs4351 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 ?0.02 ?0.015 ?0.01 ?0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 frequency(normalized to fs) amplitude (db) figure 19. single-speed (slow) transition band (d etail) figure 20. single-s peed (slow) passband ripple 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0. 6 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 21. double-speed (fast) stopband rejectio n figure 22. double-speed (fast) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0. 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 23. double-speed (fast) transition band (detail) figure 24. double-speed (fast) passband ripple
ds566f1 33 cs4351 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 25. double-speed (slow) stopband rejection figure 26. doub le-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.3 5 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 27. double-speed (slow) transition band (d etail) figure 28. double-speed (slow) passband ripple 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.2 0.3 0.4 0.5 0.6 0.7 0. 8 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 29. quad-speed (fast) stopband rejection figure 30. quad-speed (fast) transition band
34 ds566f1 cs4351 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.05 0.1 0.15 0.2 0.2 5 0.2 0.15 0.1 0.05 0 0.05 0.1 0.15 0.2 frequency(normalized to fs) amplitude (db) figure 31. quad-speed (fast) transition band (detail) figure 32. quad-speed (fast) passband ripple 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0. 9 120 100 80 60 40 20 0 frequency(normalized to fs) amplitude (db) figure 33. quad-speed (slow) stopband rejectio n figure 34. quad-speed (slow) transition band 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.5 5 10 9 8 7 6 5 4 3 2 1 0 frequency(normalized to fs) amplitude (db) 0 0.02 0.04 0.06 0.08 0.1 0.1 2 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 frequency(normalized to fs) amplitude (db) figure 35. quad-speed (slow) transition band (det ail) figure 36. quad-speed (slow) passband ripple
ds566f1 35 cs4351 8. parameter definitions total harmonic distortion + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified bandwidth (typically 10 hz to 20 khz), including distortion comp onents. expressed in decibels. dynamic range the ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. dynamic range is a signal-to-noi se measurement over the specified bandwidth made with a -60 dbfs signal. 60 db is then added to the re sulting measurement to refer the measurement to full scale. this technique ensures that t he distortion components are below the noise level and do not effect the measurement. this measurement technique has been accepted by the audio engineering society, aes17- 1991, and the electronic industries association of japan, eiaj cp-307. interchannel isolation a measure of crosstalk between the left and right chan nels. measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. units in deci- bels. interchannel gain mismatch the gain difference between left and right channels. units in decibels. gain error the deviation from the nominal full scale a nalog output for a full scale digital input. gain drift the change in gain value with temperature. units in ppm/c. intra-channel phase deviation the deviation from linear phase within a given channel. inter-channel phase deviation the difference in phase between channels.
36 ds566f1 cs4351 9. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mis- match and are measured at the parting line, mold fl ash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion/i ntrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximum material condition. dambar intrusion shall not reduce dimen- sion ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the flat section of th e lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min nom max min nom max a -- -- 0.043 -- -- 1.10 a1 0.002 0.004 0.006 0.05 -- 0.15 a2 0.03346 0.0354 0.037 0.85 0.90 0.95 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 d 0.252 0.256 0.259 6.40 6.50 6.60 1 e 0.248 0.2519 0.256 6.30 6.40 6.50 e1 0.169 0.1732 0.177 4.30 4.40 4.50 1 e -- -- 0.026 -- -- 0.65 l 0.020 0.024 0.028 0.50 0.60 0.70 0 4 8 0 4 8 jedec #: mo-153 controlling dimensi on is millimeters. parameters symbol min typ max units package thermal resistance 20l tssop ja -72-c/watt 20l tssop (4.4 mm body) package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
ds566f1 37 cs4351 10.ordering information 11.revision history product description package pb-free grade temp range container order # cs4351 192 khz stereo dac with 2 vrms line out 20-pin tssop yes commercial -10 to +70 c rail cs4351-czz ta p e & r e e l cs4351-czzr automotive -40 to +85 c rail cs4351-dzz ta p e & r e e l CS4351-DZZR cdb4351 cs4351 evaluation board - - - - cdb4351 release date changes pp3 march 2005 removed cs4351-cz ordering option. added cs4351-dzz ordering option. updated tslrd spec on page 10 . updated tdh spec on page 12 . updated vil specification on page 13 . updated legal text. pp4 july 2005 updated full-scale output specification on page 7 . updated gain drift on page 7 updated ordering information. f1 december 2005 updated status to final updated legal text table 10. revision history contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com/corpora te/contacts/sales.cfm important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semic onductor products may involve potential risks of death, per sonal injury, or severe prop- erty or environmental damage (?critical applications?). cirr us products are not designed, authorized or warranted for use in aircraft systems, mili tary applications, pr oducts surgically implanted into the bo dy, automotive safe ty or security de- vices, life support produc ts or other critical appl ications. inclusion of cirrus products in such a pplications is understood to be fully at the customer?s ri sk and cirrus disclaims and makes no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or customer?s customer us es or permits the use of cirrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cirrus, its o fficers, directors, employees, distributors and other agents from any and all liability, including attorneys? fees and costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, the cirrus logic logo designs, and popguard are trademarks of cirrus logic, inc. all other brand and pro duct names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc. i2c is a registered trademark of philips semiconductor.

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